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zachjs
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sv2v
SystemVerilog to Verilog conversion
BSD 3-Clause "New" or "Revised" License
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Converting dimensions from unpacked to packed if connected to port
#141
vogelpi
closed
3 years ago
2
Multiple issues related to structures and others
#140
flaviens
closed
3 years ago
6
Circular package dependencies when referencing the package in its own implementation
#139
flaviens
closed
3 years ago
2
usability problem: sv2v will accept any identifier name
#138
chrivers
closed
3 years ago
7
sv2v generates logic in `-E logic` mode
#137
chrivers
closed
3 years ago
3
Ergonomics improvement: trailing commas [feature request]
#136
chrivers
closed
3 years ago
2
Parser fail: integer sized by localparam
#135
chrivers
closed
3 years ago
3
Enums of custom types in package
#134
vogelpi
closed
3 years ago
5
Parser bug? "Non-exhaustive patterns in Just lhs"
#133
chrivers
closed
3 years ago
7
Warn When Parameters Omitted
#132
tornupnegatives
closed
3 years ago
1
Upload package to Hackage
#131
QuantamHD
closed
3 years ago
7
Parse error: no tokens left to parse.
#130
iamrishabh23
closed
3 years ago
6
Unable to parse sturct constant
#129
t123yh
closed
3 years ago
5
sv2v: invalid based literal digits
#128
nagendragd
closed
3 years ago
2
'0 / '1 replication issue with nested interface
#127
Mop-u
closed
3 years ago
4
Interfaces and empty output
#126
ben-marshall
closed
3 years ago
6
Yosys error with multiple wrapped casts
#125
nmoroze
closed
3 years ago
5
duplicate wire declaration
#124
Mop-u
closed
3 years ago
3
generate if/else colliding with always if/else
#123
Mop-u
closed
3 years ago
2
sv2v fails when parsing interface parameters
#122
wsipak
closed
3 years ago
3
Unexpected token 'class'
#121
s2314
closed
3 years ago
2
some assign expression in sv changed to always @(*) expression
#120
zjuwlh
closed
3 years ago
12
sv2v 7e2450e regression: extra wire declaration results in Yosys error
#119
nmoroze
closed
4 years ago
2
Support for type parameterization
#118
tomeroberts
closed
3 years ago
8
type(foo) generated in output with unknown variables
#117
rswarbrick
closed
4 years ago
5
Cast function in generate block
#116
stephenry
closed
4 years ago
6
Bug when initializing a variable in a function in a package
#115
b1f6c1c4
closed
4 years ago
1
Interface members declared inout in toplevel module.
#114
Zottel
closed
4 years ago
2
Bug when using '{} on multi-dimension array
#113
b1f6c1c4
closed
4 years ago
5
Bug when using '0 in always block on nested type
#112
b1f6c1c4
closed
4 years ago
1
sv2v: src/Convert/TypeOf.hs:181:11-37: Non-exhaustive patterns in (tf, _ : rs)
#111
stephenry
closed
4 years ago
4
Bug when using conversion twice
#110
b1f6c1c4
closed
4 years ago
1
Bug when using $unsigned in ?:
#109
b1f6c1c4
closed
4 years ago
1
Bug when using cast in generate
#108
b1f6c1c4
closed
4 years ago
1
Bug using bit selection in function in package
#107
b1f6c1c4
closed
4 years ago
1
Bug when a module with parameter type instantiate another module with two parameter types
#106
b1f6c1c4
closed
4 years ago
1
Improper handling of wide parameters
#105
b1f6c1c4
closed
4 years ago
5
Struct instance forward-declaration
#104
asinghani
closed
4 years ago
5
Duplicate struct conversion functions generated
#103
nmoroze
closed
4 years ago
2
Issue with unsized '1 in comparisons
#102
nmoroze
closed
4 years ago
13
package file not getting converted
#101
nagendragd
closed
4 years ago
24
Bug using $bits in type parameter
#100
b1f6c1c4
closed
4 years ago
1
Bug when accessing a field of a function's return value
#99
b1f6c1c4
closed
4 years ago
5
For loops in SystemVerilog not translating
#98
nagendragd
closed
4 years ago
4
Classes as namespaces not supported?
#97
fl4shk
opened
4 years ago
10
Interface port array not expanded correctly
#96
tpoikela
closed
3 years ago
19
Parameter value from interface missing in generated output
#95
tpoikela
closed
4 years ago
2
Translation of 'parameter bit'
#94
NilsGraf
closed
4 years ago
4
Conversion of '0 and '1
#93
NilsGraf
closed
4 years ago
5
Translation of 'inside' includes 1'bx
#92
NilsGraf
closed
4 years ago
22
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