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Hi @lcgamboa !
Just discovered your amazing and impressive simulator, that's very cool!
I have a question, is it cycle-accurate? Meaning that one can (or could) run at precisely 8 MHz and the output…
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Hi,
Is there a way to exit the verilator simulation from the C code whose hex is getting executed using RUN_HEX. For some reason, certain C codes are exiting but others are not. I do not know the e…
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The ARM7TDMI emulation isn't counting cycles accurately.
Need to pass most of the mgba-suite timing test
![image](https://user-images.githubusercontent.com/2903914/82161185-46044e80-98a3-11ea-8e4d…
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Find a way to make the CPU match the cycle count of TIS-100.
Problems with the current design:
1. Certain port instructions require 2 cycles because arithmetic instructions can only read registers.
…
jdryg updated
9 years ago
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Is it possible to perform cycle accurate simulation using the inbuilt simulator in migen?
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* You can use SYSCLK to get a 32-bit timer count for cycles from the system clock, so you don't have to worry about overflows
* You can use the AWU IRQ Handler to get interrupts when the AWU triggers…
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- [x] Panel to show Total number of Active Students in NG Support Support Cycle for the current Year.
- [x] Graph to show Campus wise number of Active/Placed/Dropout Students in NG Support Support Cyc…
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I'm having issues using the csv_compare method to verify that two traces are matching. I'm using Spike as a golden reference. However, Spike is instruction-accurate, while the RTL model is cycle-accur…
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# Feature request
### Route
`GET /characters/{character_id}/planets/{planet_id}/`
### Use case
`qty_per_cycle` in the extractor details, appears to currently return a value that is 5/9ths …
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Hi,
If I read the cpu emulation code correctly, divs/divu cycles are calculated simply by adding the worst case cycle count. If that's the case then the following code Jorge Qwik (ijor) will give acc…