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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched the [documentation](https://chipyard.readthedocs.io/)
### Feature…
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I like the idea of an abstract project model. I have difficulties understanding the concept of how designs and file sets are to be used in the project model and what the difference between a design an…
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As a part of my GSoC project, a common Python API will be developed to simplify the Python code in the OpenFASOC generators, starting with the Verilog generation step. This issue will be used to discu…
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## Expected Behavior
The behavioral/functional Verilog netlists should work in HDL simulation
## Actual Behavior
The behavioral Verilog netlist of High-Density standard cell `stdfrtp` has critica…
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I'm reading bluespec user guide, and found something interesting:
> In late stages of the compiler, don’t-care values are converted into specific constants. In order
that the Verilog and Bluesim sim…
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Hi,
I am using klessydra core (link of klessydra)[on](https://github.com/klessydra/T03x)) pulpino and I can run my tb from modelsim. Problem is simulation takes a lot of time (like 12 hours for runni…
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is https://github.com/efabless/caravel_user_project/blob/main/verilog/rtl/uprj_netlists.v still used?
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Missing wire declarations at the caravel and caravan module top level verilog prevent running simulations with a setting of `default_nettype none`. I do not recommend a merge until I finish a check i…
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Hello Eugene,
since the maintainers of the Rocket Chip repository dropped support for Verilator, there is a gap between HW development and FPGA simulation (and of course debugging!). Do you conside…
ncppd updated
6 months ago
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> **Describe the bug**
It looks like if I set up a task with the following in the config/task.conf:
```
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verifica…