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### Test point name
chip_sw_usbdev_stream
### Host side component
Rust
### OpenTitanTool infrastructure implemented
Unknown
### Silicon Validation (SiVal)
Yes
### Emulation Targets
- [ ] None…
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### Is there an existing core-v-mcu bug for this?
- [X] I have searched the existing bug issues
### Bug Description
In the `rtl/includes/pulp_soc_defines.svh` file [here](https://github.com/o…
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I would like to have a functionality in Yosys so that I can define certain technology boundaries (the number of logic blocks in an FPGA, the number of cells in an ASIC design), and when Yosys detects …
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Using the Gowin programmer the Runber board scans the fpga id as a GW1N-4B instead of a GW1N-4 FPGA so will not program it with code built for a GW1N-4 due to ID mismatch. I tried building the code fo…
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program-fpga-board.bat
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no files matched glob pattern "*.sof"
while executing
"glob *.sof"
invoked from within
"set sof_files [glob *.…
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This would be helpful for high-level isolated gate-level tests outside openlane or other open source PDK flows.
Examples: https://github.com/YosysHQ/yosys/tree/master/examples/osu035
We would like…
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We noticed an issue when running pacman and toggling quiet mode on and off. Occasionally we received an error about reading the FIFO. The Pixie16msg.txt file lists an error `Failed to read FIFO waterm…
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Tang Nano 20K is a development board, using the [GW2AR-18 QN88] FPGA, containing 20736 LUT4 logic cells and 15552 Filp-Flops.
Dertails can see；https://wiki.sipeed.com/hardware/en/tang/tang-nano-20k/n…
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Hello. I saw several projects aiming to integrate softcore to Arduino IDE in a way that the FPGA can then be programmed in C quite easily without much user setup.
For example the lattuino project:
…
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### Ask a question about the Sega Saturn Compatible FPGA Core
Absolute fantastic core at the moment. Is Save States planned on Saturn core in the future?