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Tried this in release 3.7 on Ultimate II, 3.10a on Ultimate 64 Elite and 3.10e on Ultimate II+L:
Using Commodore MPS, Epson FX-80/JX-80, IBM Graphics or IBM Proprinter emulations, once a printed li…
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Hi,
Xelab is failing silently (segment fault, core dump).
I'm trying to figure out what about my testjobs is causing it...
In the hunt to try and find any clues, I turned on `xelab`'s verbos…
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I have this design where I use SPI block that is "hardcoded inside the FPGA". I don't have the design of this element, but I am able to use it successfully once my bitstream file is uploaded to the FP…
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(x-post to BSG Manycoree)
It seems unnecessary to have $display statements enabled for every simulation run. Printing information on every run can slow the simulator down, or clog with unnecessary in…
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### Did you check docs and existing issues?
- [X] I have read all the LazyVim docs
- [X] I have searched the existing issues of LazyVim
- [X] I have searched the existing issues of plugins related to…
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Hi,
it would be greate to have SystemVerilog's immediate assertion statements working in iverilog.
The following example respondes `assertion_example.sv:5: sorry: Simple immediate assertion statem…
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These are the VHDL kinds parsed in the latest implementation of ctags:
```c
static kindDefinition VhdlKinds[] = {
{true, 'c', "constant", "constant declarations"},
{true, 't', "type", "type de…
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when I use verilator api `contextp->internalsDump();` to print all scopes and variables' name, I found output's escaped identifiers have some difference with "IEEE Standard for SystemVerilog--Unified …
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I am trying to run the verification for the core. I have installed the toolchain as instructed. However, while trying to install and build spike simulator. I am seeing these issues. I have gone …
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Hello,
I am enjoying gently diving into llhd as hobby during lockdown, and in that sense, my reading of the paper and the information out there might not be as thorough as it could be, so please ig…