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This could be a fun bit of data for each language.
Inspired by https://github.com/o2sh/onefetch/issues/1308
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Coq sometimes misinterpret Verilog HW description language files as being Coq prover language files.
There has been a number of issues opened related to this. But all of them has been closed without …
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I have taken a quick look into supporting the Synopsys VCS simulator.
It looks like similar to Cadence's `cds.lib`, VCS needs a file `.synopsys_vss.setup` for the library name-to-path mapping. http://…
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Hi, nice project you got there!
I am trying to run the code with basic tests, to further verify using UVM since I'm currently working with the tool.
However, when running only the RTL in Xcelium t…
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## **Describe the bug** - _A clear and concise description of what the bug is_.
There appears to be a problem with the way this extension works with the vscode config parser.
In that, unlike other…
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Yosys is currently missing a [FIRRTL](https://github.com/freechipsproject/firrtl) frontend. Verilog is not ideal as an interchange format, and nobody seems to be using BLIF much these days. It is no…
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Type: Bug
I cannot access servers with ssh.
VS Code version: Code 1.89.1 (dc96b837cf6bb4af9cd736aa3af08cf8279f7685, 2024-05-07T05:16:23.416Z)
OS version: Linux x64 5.15.0-102-generic snap
Modes:
…
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### Example
```sv
module m (
input [1:0] i1,
i2,
output [3:0] o
);
assign o = i1 + i2;
endmodule
```
Compile using:
```sh
verilator --binary m.sv
```
### Current O…
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Like `icarus verilog`
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The purpose of this issue is to gather a list of projects that we can use as tests for ghdl's synthesis features.
- https://www.gaisler.com/index.php/products/processors/leon3
- [antonblanchard/m…