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I am a beginner in NoC and I am more familiar with HDL languages. I downloaded the run_dir folder according to the Quickstart regression using Git Bash. I don't quite understand the purpose of the fil…
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**Is your feature request related to a problem? Please describe.**
To be more user friendly, PSL assertions could be added to waveform dump (GHW only since FST and VCD).
**Describe the solution yo…
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`/build/cpprest-2i1wUL/cpprest-2.10.2/Release/src/websockets/client/ws_client_wspp.cpp:315: web::websockets::client::details::wspp_callback_client::connect_impl():: [with WebsocketConfigType = websock…
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### Answers checklist.
- [X] I have read the documentation [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/) and the issue is not addressed there.
- [X] I have updat…
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### Answers checklist.
- [X] I have read the documentation [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/) and the issue is not addressed there.
- [X] I have updat…
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I dont know what happened ,if i use lua-nginx-module on nginx:1.16.1 verison
when i start nginx:1.16.1
2020/05/30 05:21:14 [alert] 73242#0: worker process 74783 exited on signal 11
2020/05/30 …
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This is not a bug, I would just like to discuss some of my findings.
I choose VexRiscv, since it seems to be the the most prominent FPGA implementation of RISC-V.
I did not synthesize VexRiscv mysel…
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Optimizations that can be done:
1. `cocotb` optimizations
- [x] move clock generation to HDL
2. TO BE ADDED
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hey @gmacgilchrist, I've accomplished very little in the last week cause I've had trouble understanding and implementing a lot of the recommendations from my previous issues. In order to gather my tho…
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I am trying to move ara on VCS, but met too many errors, and they are hard to fix.
Do you have the correct Compilation Options on VCS or irun? Or a script of running by VCS?
These are examples of…