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Hi,
I am trying to build the EL2 design for the Intel Cyclone 10 GX FPGA. This is using the free license within Quartus Prime Pro 21.2.
I am having issues with the `el2_param.vh `and `el2_pdef.vh`…
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I tried to run a simulation of `femtorv32_quark.v` using the Vivado simulator, because I my SoC gets past synthesis well, but gets minimized to nothing during implementation, I do not know what is goi…
jeras updated
2 years ago
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**Describe the bug**
I want to see my rram module in schematic view. "Schematic view" didn't output an image, while dev tools returned `console.ts:137 [Extension Host] stack trace: RangeError: Maximu…
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I can see that the way hdlConverter works is that it first passes the code through a preprocessor.
Then produces and AST from the resulting text.
This preprocessor 'flattens' the code, replacing `…
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Tried this in release 3.7 on Ultimate II, 3.10a on Ultimate 64 Elite and 3.10e on Ultimate II+L:
Using Commodore MPS, Epson FX-80/JX-80, IBM Graphics or IBM Proprinter emulations, once a printed li…
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We have started to do some work but we didn't have an issue for it so I'm creating one.
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> Hi - can you please add support for SystemVerilog files (and maybe VHDL files too)? this is the main language we use
- from [jonnyboynewton](https://github.com/jonnyboynewton)
- [original issue]…
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These are the VHDL kinds parsed in the latest implementation of ctags:
```c
static kindDefinition VhdlKinds[] = {
{true, 'c', "constant", "constant declarations"},
{true, 't', "type", "type de…
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This is a tracking issue for the first steps towards implementing a hardware description language for Tydi types.
Currently the Tydi crate provides modules with the logical and physical stream type…
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In Clash `master` and `1.6`, there is a bug when generating HDL under very specific conditions. Only with GHC 9.0.2 (out of the versions we test in CI), with multiple hidden enabled, an annotation fro…