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I'm a newbie to Verilog but I'm seeing a difference between simulations run with iverilog 12 and ISim (14.7) and I think it may be a bug in iverilog. I'm attempting to simulate a verilog module I'm d…
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Hi,
I am trying to build the EL2 design for the Intel Cyclone 10 GX FPGA. This is using the free license within Quartus Prime Pro 21.2.
I am having issues with the `el2_param.vh `and `el2_pdef.vh`…
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I cannot get Digital Simulations to work in Qucs-S. I installed Icarus Verilog, FreeHDL. I believe all required programs have been installed but still no luck.
Digital Simulations work in Qucs 0.0.…
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This was tested on latest Git master.
I tried the following shorter examples **not** causing a crash:
- generate case string + processes to print MODE,
- generate case string + entity instance wi…
jeras updated
9 months ago
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the **sg13_lv_nmos** model should accept an `m` parameter in spice-simulation. at least the Xschem-symbol has this parameter and any MOS-device should, because its a spice-standard. but i ngspice-simu…
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Conditional jump (JR) is not working.
Test rom:
```
// Check conditional jump
// https://www.asm80.com/onepage/asmz80.html
//0000 00 NOP
//0001 37 …
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Vadim,
I have a big wish.
The life would be much easier if there would an entry field for model cards which can provided by include a file. I made a sketch:
![Bildschirmfoto vom 2023-12-26 19-18-56…
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Hi,
The litexGen isn't a self contained runner, it need some argument and anditional scala file to generate.
For instance, https://github.com/litex-hub/pythondata-cpu-naxriscv/blob/m…
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I'm interested in getting litex to work fully with the tang primer 20k, so I can try some riscv rust programming on it. Without the dram things are kinda limited (the dram is way overkill, but I want…
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Verilator is failing a simulation that Questa and VCS are passing. I eventually tracked the discrepancy down to a cache with four ways, each containing tag memories. The Verilog writes to the memory…