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Hi wujian100 owners, thanks for your contribution to open the source code of wujian.
But I met some trouble when I want to know more about its architecture or details inside.
Could you release some …
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Hello,
can you please add support for icebreaker board?
it's ICE40 based open hardware board readily available for reasonable price through several vendors.
It's also fully documented here: https:/…
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I want to sim the SpinalSimSpiXdrMaster.scala,but some problem:
` test(prefix + "compile") {
doCompile()
}
for (cpol
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Hi Charles,
To follow up on the discussion in this pull request #115
As I understand it, when the processor is in baremetal mode, and makes a store to a non-peripheral address, the request will …
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My Linux verilog generating environment is sbt 1.10.0 (Red Hat, Inc. Java 11.0.23). when using sbt "Test/runMain vexiiriscv.Generate" to generate verilog, the terminal reports the error information as…
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I recently tried to create a Register with a default Bool value like
```
val first = RegInit(False)
```
but accidentally used `Reg` intead of `RegInit`. It seems like SpinalHDL interprets True/Fal…
dnltz updated
10 months ago
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I try to generate verilog by using the intelliJ IDEA, sbt 1.10.0 (Oracle Corporation Java 1.8.0_301) but now it reports
C:\Users\pzhao\Downloads\VexiiRiscv-dev\ext\SpinalHDL\core\src\main\scala\spina…
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Since the P and V extensions have overlapping functionality, yet are largely suited to different application domains, they are considered mutually incompatible. This avails each extension of the other…
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Hi,
Back in VexRiscv there are options like `NoMemory` and `NoWriteBack` that can be toggled for shallower pipeline structures (below 5 stages), which is pretty useful in reducing FFs.
I noted t…
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This has been going on for over a year now, when I work between PCs, Windows updates, or anything changes etc...
Uninstall everything (sbt, all javas, IntelliJ etc...)
Install sbt-1.8.2.msi
Ins…