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Hi all,
After a looong time spent on ironing-out some issues, I finally have a working PULPissimo based SoC with 5 hardware accelerators. I've implemented a few applications so far with the design,…
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http://covered.sourceforge.net/
http://www.asic-world.com/examples/systemverilog/index.html
https://github.com/FPGAwars/FPGA-peripherals/wiki/Asynchronous-serial-receiver-unit
https://verificationa…
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@cliffordwolf @FSMaxB @gordon-quad
We need more examples, what do you all think we need to add? (hoping we could brainstorm, I also have some time this weekend to create stuff)
Some ideas:
- C->Ver…
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Hello,
Thank you for making this extension, it is very neat and useful.
I was looking at the code in sources/scripts/utilities/cryptography.js and it appears that your key derivation is **not su…
ghost updated
2 years ago
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Is the verilog from "make verilog" in vsim supposed to be synthesizable like in other Rocket repositories? I can't find the top level for the synthesis. Also, are you planning to release a template de…
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**Is your feature request related to a problem? Please describe.**
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**Describe the solution you'd like**…
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In light of the growing frequency and scale of rollback attacks, a recent example being the [attack on ETC announced by Coinbase](https://blog.coinbase.com/ethereum-classic-etc-is-currently-being-51-a…
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Idea: Add a counter to the hardware that stores it's value within the secured boundary. The counter can only be increased and not be decremented or overflow (=fail instead of overflow).
### Usecase…
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### Project Name
DRV64IMZicsr
### Description
DCD’s RV64IMZicsr RISC-V Core
The DRV64IMZicsr is a 64-bit RISC-V CPU with M, Zicsr extensions and External Debug support. As a part of the DRVX Core …
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At RWC I was chatting with [Wei Dai](https://twitter.com/_weidai), who mentioned (I think? I talked to a lot of people) that Anoma (was it?) are working on a specification called Vampir (? I'm bad at …
str4d updated
2 years ago