-
It would be good to add additional examples to the optimization docs. Possibilities are:
- level set optimization
- basic shape optimization (e.g. diameters and origins of circles)
- more sophist…
-
~~Exploring master thesis topic!~~ With **Honors** bsc, also msc **With Honors** potential! Only thesis grade needs to be high. _Zero_ courses to be done. 12 months of msc dedicated focus. [Honor thes…
-
## Location
* Lakeview 1, 19 To Huu Street, Thu Thiem Ward, Thu Duc City, Ho Chi Minh City
* Remote
## Salary Expectation
* Nego
## Requirements
- Excellent analytical and problem-solvin…
-
Hi,
I've been working with SpinalHDL for a few months and am inspired by the design of NaxRiscv. I aim to deepen my understanding by building a toy CPU from scratch. While I appreciate the complexi…
-
**Title: The Autopoietic Meta-Meme Coin for DAO AI**
Imagine a digital asset that's not just a currency but a living entity within the blockchain ecosystem. We're introducing the **Meta-Meme Coin**, …
-
Adding/Finishing ECP5 support would be interesting since could provide a FOSS solution (Core + Toolchain) for a SATA controller and would also be directly useful for projects like [Linux-on-LiteX-VexR…
-
Im very new to VHDL
but i dont know how to use this!
have you got a basic setup i could use?
id like to use 4 switched, 1 and 2 to increase the address, and 3 and 4 to set a value
i have 4 …
-
Hi,
thanks for sharing your project and for the explanation write-up.
Your design uses 2 MCU pins to drive one TIC (tested IC) pin. I was wondering whether this could be simplified and only one MC…
-
-
This is a language feature proposal.
Incorporating the ability to publish projects and add dependencies similar in spirit to Rust is a great addition to Veryl. However, one current limitation, it s…