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RSD looks like it would be a super interesting addition CPU core option for the [LiteX Ecosystem](https://github.com/timvideos/litex-buildenv/wiki). LiteX already supports multiple different RISC-V co…
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Setting up the Xiling Spartan-6 involves installing a VM which is capable of running ISE 14.7.
From here we can write the firmware in VHDL if we connect the JTAG to the FPGA.
The development ar…
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I couldn't find pin assignment of JTAG_TAP for de0_nano from orpsoc-cores/systems/de0_nano/data/pinmap.tcl. Does that mean I couldn't use OpenOCD to write program to RAM via JTAG?
This seems to expla…
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I'm new to ESP and heterogeneous SoC design as well. I'm very interested in using ESP for our research project.
But we don't have any supported boards now.
We would like to use ESP for the Ultra96…
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Hello VexRiscV Community,
I've been trying to run my VexRiscV project on my DE0-Nano FPGA board and encountered two issues. I aimed to configure the project for a Cyclone IV FPGA following the guid…
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Greetings,
I wanted to report an issue I was having using this go package. I recently got some used boards of ebay (claimed they still worked) to practice hacking on and the like. The reason I grab…
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Hello,
I've successfully synthetized the whole VHDL code to fit a spartan-6 and simulated it with Xilinx tools.
Now I would like to put my own sketch in the softcore program memory.
But to start wi…
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I tried to use your project and make some modifications in order to measure the frequency of an ADC signal input which goes from 1Mhz to 100MHz.
How can I proceed ?
What is the utility of using the …
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Hi all,
The HWPE behavior between simulation and FPGA is different. I've tried it with pulp_soc v2.1.0, v3.0.0 and v3.0.1. They all show the same problematic behavior so far.
**INFO:** I'm using…
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Hi Skordal, I would like to thank you for designing and uploading the Potato SoC, I admire your work and I know how time consuming it can be to maintain and solve all the issues and users requests. …