-
```
What steps will reproduce the problem?
1. ./odin_II.exe -V top_UART.v -a sample_arch.xml
2. Run in Icarus Verilog and the verilog file compiles and runs
3.
What is the expected output? What do yo…
-
### Problem description:
I usually create my testbenches so that the signal generation section uses some idiom for "wait for the next clock rising edge" rather than waiting a fixed amount of time. T…
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objcopy can produce verilog output directly from ELF files with "objcopy -O verilog inputfile outputfile".
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There are many unsupported constructs in Verilog that I faced while trying to run a verilog design through Odin. I have created a micro testcase for each of them and they can be found at: https://g…
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Hi Nic30:
Is it possible to instantiate a VHDL or Verilog IP as a black-box component like [Spinalhdl](https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Structuring/blackbox.html)? Thanks.…
-
```
What steps will reproduce the problem?
1. ./odin_II.exe -V top_UART.v -a sample_arch.xml
2. Run in Icarus Verilog and the verilog file compiles and runs
3.
What is the expected output? What do yo…
-
```
What steps will reproduce the problem?
1. ./odin_II.exe -V top_UART.v -a sample_arch.xml
2. Run in Icarus Verilog and the verilog file compiles and runs
3.
What is the expected output? What do yo…
-
```
What steps will reproduce the problem?
1. ./odin_II.exe -V top_UART.v -a sample_arch.xml
2. Run in Icarus Verilog and the verilog file compiles and runs
3.
What is the expected output? What do yo…
-
I'm having issues getting my code to pass the test bench. I thought we went through all my code and validated it in lab but I guess there are some errors still. Could you take a look at my code? I've …
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There are some parsers for HDL however all of them have some ridiculous weakness.
I would like to use [hdlConvertor](https://github.com/Nic30/hdlConvertor) because I know that the Python dependency…
Nic30 updated
5 years ago