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Hi, i was trying to generate a basic cache (the one described in README file). This is the config file:
```
# Data array size
total_size = 1024
# Data word bit size
word_size = 8
# Number …
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I've cloned latest commit and installed in Ubuntu20.04
Used following command to generate sram module:
```
python3.8 compiler/openram.py macros/configs/sky130_sram_4kbyte_1rw_32x1024_8.py
```
B…
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Hey Matt,
I was trying out the Sky130 branch. When I was running OpenRAM with this config,
```
word_size = 2
num_words = 16
tech_name = "sky130"
nominal_corner_only = True
output_path = "temp"
…
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hi all,
In scn4m_subm tech, i want to implement a 2rw-dual port memory, which means,
num_rw_ports = 2
num_r_ports = 0
num_w_ports = 0
but it shows errors as,
ERROR: file delay.py: line 882: S…
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![image](https://user-images.githubusercontent.com/54830019/174438486-c704a53a-25ab-4927-978b-275a2adced06.png)
![image](https://user-images.githubusercontent.com/54830019/174438522-0c86b799-8fee-4…
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Hello,
I am currently seeing DRC violations with an OpenLane design that has OpenRAM macros. Is this normal? What can I do to fix this?
Thanks,
Mousa
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From the waveform I see there are 2 access latency when reading the sky130_sram, can I have 1 clock latency sky130 sram?
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https://github.com/Xyce/Xyce
> Xyce (zīs, rhymes with "spice") is an open source, SPICE-compatible, high-performance analog circuit simulator, capable of solving extremely large circuit problems by s…
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I tried OpenRAM and after [comment ](https://github.com/VLSIDA/OpenRAM/issues/146#issuecomment-1191704852)decided to make clean installation.
My steps are:
```
sudo git clone https://github.com…
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