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The submodule "litex @ fbadfa1" uses an outdated URL in .gitmodules:
```
[submodule "litex/soc/software/compiler_rt"]
path = litex/soc/software/compiler_rt
url = https://git.llvm.org/git/compile…
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I get the following error when building hps_accel:
```
6.2. Continuing TECHMAP pass.
Using template VHI for cells of type VHI.
Using template VLO for cells of type VLO.
No more expansions possi…
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No mention of it being detected as a TDP pattern by Vivado (when WRITE_FIRST it is detected)
Used in artiq/suservo:
https://github.com/m-labs/artiq/blob/7d4a103a43a2cc4c1787eaa7aff2f37de8738050/…
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Trying to synthesize the generated Verilog with yosys fails:
````
$ yosys -p "read_verilog TangNano9k.v; synth_gowin -json TangNano9k.json"
...
2.2.2. Analyzing design hierarchy..
Top module: …
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To use litex and vexRiscv there are various build tools required.
The aim for this repo is to build all the required tools into one or more containers to allow quicker build and automated testing o…
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Hey, despite Symbiflow mentioning ice40 support based on icestorm being supported, there seems to be no mention of it in this repo.
Is this anywhere on the radar?
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## Environment
Lenovo Thinkpad W520. _Optimus is Enabled._ I have a dual-monitor setup. Thanks to how the buses are laid out, Intel GFX _or_ NVIDIA can use the built-in first monitor, but only NVID…
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Hello there,
I am trying to get timing data for modules without assigning/requiring IO placement.
For ECP5 out of context has worked great. Can the same be done for iCE40?
I tried `nextpnr-ic…
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Many fabrics have simple 2-input 1-select line muxes located in the SLICE site. These appear in 7-series (MUXF7, MUXF8), US+ (MUXF7, MUXF8, MUXF9) and in QuickLogic EOS S3 (mux controlled by QDS and …
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## Steps to reproduce the issue
Unpack the attached zip.
Run the command in `run` first using a Yosys compiled with clang, then with a Yosys compiled with gcc. The results will be different. …