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Im using systemrdl to implement my cores CSRs, with a generator that consumes a rdl file and compiles it to systemverilog files and thats working fine.
Now lets say I have 3 cores: A, B and C. The …
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I used the DV to test my design of RV64IMC, and i worked so good. Now i want to test my machine mode csr register implementation.
When i try to run the csr test, this error keeps showing up, what sho…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- [X] Y…
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Hi! First of all, thanks for the great work so far!
I would like to add a generator for CMSIS SVD files (a register description format for debugging, see [here](https://www.keil.com/pack/doc/cmsis/…
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### Bug Description
This Issue is motivated by pull-request #150, which includes update to [gen_csr_test.py](https://github.com/openhwgroup/cve2/blob/d2a1be82ef5d68a179cef1972a2f304cee459ce8/vendor/g…
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The reason i am asking this
i have try validation/csr and fail to pass
the csr using https://csrgenerator.com/ or openssl commond line both fail to pass
https://api.zerossl.com/validation/c…
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HI,
Please find the below list of CSRs which has discrepancies between CVA6 and spike
Sl no | Name | Address Offset | Width | Access Type | Reset…
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**Describe the bug**
After recompiling the binaries from source for AVX-512 cores Octopus no longer runs as normal, producing error:
'Phred: negative error
[2024-07-15 12:55:12] probability -…
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根据我目前的信息，有些库是兼容0.7的，有的是采用 **intrinsic**，很疑惑，到底该怎木选择？
这里用的是 **intrinsic**
https://chromium.googlesource.com/libyuv/libyuv/+/refs/heads/main/source/row_rvv.cc
这里采用纯汇编的方式实现
https://github.com/FFm…
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@BarakKatzir has been developing the [`types-scipy-sparse`](https://github.com/BarakKatzir/types-scipy-sparse) stub package for `scipy.sparse`. A large portion appears to more complete that the `scipy…