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### Before start
- [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。
- [X] I have searched the previous issues and did not find anything releva…
stwjt updated
1 month ago
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**Is your enhancement proposal related to a problem? Please describe.**
Currently, `fpga_load()` expects the entire bitstream to be stored in a contiguous memory region. Because bitstream files tend …
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The AMDC hardware supports two encoder ports, but the FPGA has been configured for 1.
In the block diagram, the inputs are all going to one encoder block, with the second set being labeled as "alar…
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Hi,
Here is were i'm reporting the FMax mesurments and progress.
For VexiiRiscv (set as toplevel, after some tunning) with :
- RV32IMACSU + 4\*4KB I$ + 4\*4KB D$ + D$ hardware prefetcher + st…
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When I use the latest [marcos_extras](https://github.com/vnegnev/marcos_extras) such as branch [vn/mimo](https://github.com/vnegnev/marcos_extras/tree/vn/mimo)
or a self compiled FPGA bit file, [vn/…
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Hello. I have been "hobby" working on a KL10-PV emulation of the real hardware in Verilog for a while now. I hope someday to boot TOPS-20 on this in simulation and then make it run in an FPGA. I'm a s…
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I have a CNN model. I used the hls4ml and all file and bitfile generated completely. Now I used the deployment code to implement on FPGA(ZCU104), the prediction output of FPGA is always Zero.
**Tot…
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Hi, If I build rom with parameter DEFINE SKIP_MEM_TEST 1 than memory test is skiped, but GS doesn't play sound. It looks like don't receive data.
[gs105bnotest.zip](https://github.com/psbhlw/gs-firmw…
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Tang Nano 20K is a development board, using the [GW2AR-18 QN88] FPGA, containing 20736 LUT4 logic cells and 15552 Filp-Flops.
Dertails can see;https://wiki.sipeed.com/hardware/en/tang/tang-nano-20k/n…