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```
Could you please add support for highlighting Verilog and System-verilog ?
```
Original issue reported on code.google.com by `alertj...@gmail.com` on 26 Sep 2013 at 2:54
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With system verilog being used more and more, this might be a useful addition
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Hello,
I want to use HDL AST to generate **Verilog (not System Verilog)**, but I am **worried that whether the converted file will have System Verilog specific syntax**. I see the class name in the …
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When running yosys -p "read_verilog -sv generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.sv"
on my newly generated System Verilog code, after finally extending Yosys for the new syntax…
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Just like the VHDL or Verilog Generation, does SpinalHDL generate SystemVerilog codes and needs some basic info about using the verification environment in SpinalHDL?
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### What's hard to do? (limit 100 words)
Making the generated Z3 code independent and provable standalone. There are three things I would like to address:
1. The assertion node is unhandled whil…
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how to configure Verilog/System Verilog to support in Emacs lsp-mode?
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How can use Verilog/system-Verilog testbench to verify the function of USB device?
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The new verilog backend seems to support system verilog, based on the feedback I'm getting from the editor. But when trying to use structs I'll get the message that structs are not supported during co…
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```
Could you please add support for highlighting Verilog and System-verilog ?
```
Original issue reported on code.google.com by `alertj...@gmail.com` on 26 Sep 2013 at 2:54