-
We'd like to allow both SystemVerilog and VHDL test benches in our project. From #297 I learned that
```python
from vunit import VUnit
```
should be used for VHDL, and
```python
from vunit.veri…
-
## Is your feature request related to a problem? Please describe.
Being an EE undergraduate student, I'm always on the lookout for the simulation of Digital Electronics and their programming in Ver…
-
When i'm trying to build the tests, i meet following errors. It seems that there are syntax error in the verilog codes
iverilog -o build/sim.vvp -s gpu -g2012 build/gpu.v
build/gpu.v:187: error: P…
-
Hi!
Firstly, excellent work on Moore and LLHD.
It might be [worth checking out UHDM](https://github.com/chipsalliance/UHDM) developed as a layer between [Surelog](https://github.com/chipsallianc…
-
```verilog
module dummy_module_name #( parameter WIDTH = 4, parameter LATENCY = 0 )
(
input wire clk,
output wire out
)
localparam LP = WIDTH / LATENCY * L…
-
## Description
Write a testbench for the SystemVerilog code that is accepted in issue #1. Make sure to test it with RTL simulation and verify with the code from the issue.
## Understanding code
M…
-
Most of configurations in RC is untested. Making RC almost impossible to accept RTL changes to new RV extension from community.
0. Currently Makefile-based testing decoupled Chisel elaboration, FI…
-
Hi
I am wondering if there is a plan to support compilation of the model to SystemVerilog using the -sv flag from sail.
I have attempted extending the makefile with this command:
`sail -sv $(SAI…
-
Hi,
I'm trying to generate an SoC with Chipyard and then pass the design to OpenLane for automated RTL-to-GDS.
I'm running the simulation for the example RocketConfig and then attempting to use …
-
Hello.
I have been using LibSystemCTLM-SoC to cosimulate my Zynq designs for behavioral/RTL simulations.
I use generated simulation scripts and files from Vivado and replace the "processing_syst…