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We'd like to allow both SystemVerilog and VHDL test benches in our project. From #297 I learned that
```python
from vunit import VUnit
```
should be used for VHDL, and
```python
from vunit.veri…
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## Is your feature request related to a problem? Please describe.
Being an EE undergraduate student, I'm always on the lookout for the simulation of Digital Electronics and their programming in Ver…
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## Description
Write a testbench for the SystemVerilog code that is accepted in issue #1. Make sure to test it with RTL simulation and verify with the code from the issue.
## Understanding code
M…
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`invalid-system-task-function` states:
> Checks that no forbidden system tasks or functions are used. These consist of the following functions: `$psprintf`, `$random`, and `$dist_*`. As well as non-L…
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With respect to the following comments:
```
// Simulation problem
// Sometimes (like in MULM1) DBH is not set. AU is used in these cases just as a 6 bits counter testing if bits 5-0 are zero.
/…
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Hi,
I'm trying to generate an SoC with Chipyard and then pass the design to OpenLane for automated RTL-to-GDS.
I'm running the simulation for the example RocketConfig and then attempting to use …
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When i'm trying to build the tests, i meet following errors. It seems that there are syntax error in the verilog codes
iverilog -o build/sim.vvp -s gpu -g2012 build/gpu.v
build/gpu.v:187: error: P…
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Hello.
I have been using LibSystemCTLM-SoC to cosimulate my Zynq designs for behavioral/RTL simulations.
I use generated simulation scripts and files from Vivado and replace the "processing_syst…
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(Note that I program in SystemVerilog, not VHDL)
Hello,
I'm trying to simulate your 'ym2149_audio.vhd' in ModelSim. Your core appear to properly receive my command and the PCM out does change …
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```verilog
module dummy_module_name #( parameter WIDTH = 4, parameter LATENCY = 0 )
(
input wire clk,
output wire out
)
localparam LP = WIDTH / LATENCY * L…