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## Vivado simulation crashes due to Verilog arrays defined in LSB format in cv32e40x_alignment_buffer.sv
### Component
**Component:RTL**
rtl/cv32e40x_alignment_buffer.sv
### Steps to Repro…
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I modified `t/t_class_param.v` to showcase this issue.
The first issue is, that the parameter for a parameterized type is ignored, this part of the code properly fails.
I wrapped some code with `/…
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Hi! We've been using this library with expect tests as per [this tutorial](https://blog.janestreet.com/using-ascii-waveforms-to-test-hardware-designs/), and it's a huge step up from having to manually…
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Hi,
Thank you for updating the new version of openwifi-v1.4.0. Recently, I encountered some problems while build FPGA of openwifi-v1.4.0.I am experimenting with Ubuntu 2018.The version of VIVADO I us…
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Hello, we found a puzzling problem in the actual operation of the project. In order to ensure the simplicity of the code, we have merged the part of the inertial delay. In theory, this approach will n…
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Tests are seg faulting under both RHEL7 and RHEL8 at what seems to be random parts of the simulations
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Currently, TerosHDL saves the RustHDL project file `vhdl_ls.toml` as `.vhdl_ls.toml` in the user's home directory (`~` on Linux and `C:/Users/` on Windows). This is fine for one-off development, but c…
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Hi,
Thanks for your efforts.
I wanted to run a simulation as mentioned in http://sergeykhbr.github.io/riscv_vhdl/verification_page.html#sim_tb_link and unable to find the mentioned testbench file …
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Hi,
Just installed ESP with Xilinx and Modelsim, and tried the simplest configuration with Leon3 and no caches. I skipped the make llc-hls and l2c-hls as indicated in the tutorial, since I am not…
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## Observed Behavior
Simulator fails to build with the following output:
```
test@riscv-dev:~/ibex$ fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system --RV3…