-
Hi,
I am trying to replicate the repo on an ARTY-A7-100T board.
I ran make CONFIG=rocket64b1 BOARD=arty-a7-100t flash. and it has completed succesfully.
**
**
Then I tried to run xsdb to downl…
-
Hi. When trying to build the demo I get:
```
usb_main.c:20:10: fatal error: litesdk_timer.h: No such file or directory
20 | #include
```
It looks like the repo expects a submodule `git@gi…
-
Hey again,
This is a followup from #283, since I've got access to a full Vivado license.
Adding support for the dual QSPI flash on this board was more difficult than I had expected, so I'll try …
-
Whenever I build the bitstream for the Arty-A7 35T I receive the warnings:
WARNING: [Synth 8-3331] design VexRiscv has unconnected port iBusWishbone_ERR
WARNING: [Synth 8-3331] design VexRiscv has…
-
**Describe the bug**
Project fails to build using `Sysbuild` with an out of tree board.
This issue was first posted #53780 and fixed with #56801. The issue appeared again at aff9683387ff3fc6a88cb1…
-
Hello,
I need to configure PMP secure memory areas in a binary. I have to do it on the Vexriscv RISC-V processor with the Secure variant which contains the 16 PMP registers. I don't see how to set…
-
Hi! My issue in #5 has been resolved. Thanks to the reference you gave.
Now the program loads successfully. But now the issue is that there is no display on the LCD screen. I think It doesn't detec…
-
Hello , I'm an Japanese software engineer, I used to work for DEC Japan.
I supported RSX-11M operation system and I did programming on it in Macro-11 and FORTRAN.
I'm VERY VERY interested in your …
-
When calling `connect_to_resource` on a SPIRegisterInterface (and probably also on the other SPI*Interface:s), I get the following error:
```
AttributeError: 'SPIRegisterInterface' object has no a…
-
Hi,
I am reading your book and I am trying to run simulation on Vivado 2022.1 for CH1's logic_ex example. However, it fails on checking and show "FAIL: AND Gate mismatch". I tried to set Project de…