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Hey, I want to build litex project with ethernet peripheral. I succesfully builded project and generated bit file. I'm trying to loading boot.json file but I got this error.
![image](https://github.…
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the issue metioned on:
https://github.com/litex-hub/linux-on-litex-rocket/issues/40#issue-2324887509
i found the arty.dts had a node with interrupts-extended:
```
L1: interrupt-controller@c0000…
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We are trying to use our 6T SRAM design instead of the BRAM for simulation. I understand that we would still need the BRAM to copy the image(vmem or elf) into the memory. My idea is to copy the …
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Hi
I can use VectorBlox-SDK to generate ultralytics.yolov5m.relu.vnnx correctly,but my device can't read ultralytics.yolov5m.relu.vnnx
![3](https://github.com/user-attachments/assets/7d661ba4-5b44-4…
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Hi Seb,
Thanks for all the great work you've done. I'm wondering about the device tree source file that you've written. The FPGA configuration that I'm using will not enable some of the peripheral…
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First, let's start with a diagram of how RocketChip is wired into LiteX:
![](https://user-images.githubusercontent.com/1450143/102630245-9bac1c80-414c-11eb-92c9-311fd4e06bea.png)
Rocket has a ME…
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- [ ] Blinky
- [ ] Counter
- [ ] Ibex
- [ ] LiteX?
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The bit stream was loaded on to the board and it was hang at Liftoff while loading firmware to the board with the command ("litex_term /dev/ttyUSB1 --kernel=firmware.bin"). Here I'm using nexys4ddr bo…
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Hi,
I am trying to use OpenCL SDK 17.1 (Quartus Standard ) with De1SoC
I am having a couple of problems
OS Ubuntu
Intel SDK installation
Quartus Prime Lite 17.1
Intel FPGA SDK for OpenCL 1…
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Hello David,
I am interested in testing your network on the XC7Z020 SoC which is smaller than the XC7Z045 you were using. I can see that the main issue is with the bram utilization.
Do you have an…