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## Steps to reproduce the issue
I have two (intended-to-be) identical designs, with a key difference in syntax noted by a comment in each of the designs:
```
// broken.sv
`default_nettype none…
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Hello,
I am using Icarus Verilog for simulations using cocotb testbench. The iverilog version is 11.0 stable. Running on Ubuntu 18.04LTS.
I get an error when I run the simulation on Icarus Veril…
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MAINTAINER EDIT: ISSUE REOPENED BECAUSE OF THIS COMMENT: https://github.com/Cloud-V/Fault/issues/13#issuecomment-753776273
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I am trying to run [spm](https://github.com/Cloud-V/Fault/blob/master/T…
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First of all, let me thank everybody contributing to this fast hardware simulator. Me and my colleagues use many of Verilator features and that's why we would like to also contribute to the community.…
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First, thanks a lot for this great and very powerful Verilog/SV simulator!
We are currently integrating Verilator into DaCe as part of the RTL CodeGen backend (https://github.com/spcl/dace). For th…
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I would like to use Verilator to perform Single-Event Effect (SEE) fault injection, such as Single-Event Upsets in flip-flops and Single-Event Transients in gates*, to determine a failure rate on a fu…
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https://github.com/antonblanchard/microwatt
> A tiny Open POWER ISA softcore written in VHDL 2008. It aims to be simple and easy to understand.
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Hi everyone,
I have been trying to synthesize rocket core with different configurations on FPGA to characterize their size in terms of resources and the impact of each added block or parameter. How…
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This is a follow-up to #337 . Now that we can generate Verilog from code in standard using memories I have noticed the following issues:
1) In the generated Verilog sometimes the signal "reset" is …
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Hi.
I am using the Briey SoC included in the demo with an Anlogic EG4S20 (Sipeed Tang Primer board), clocked at 50MHz.
[Briey SoC on Sipeed Tang Primer](https://github.com/jmio/testvex)
With th…