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## Observed Behavior
I wanted to start the verification for xrun. Whenever I execute make i get this message:
```
$ make TEST=riscv_machine_mode_rand_test ITERATIONS=1 SEED=1 COV=0 SIMULATOR=…
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Please try to make sure that everything we push is at least compiling.
[ 33%] Building CXX object CMakeFiles/xrt.dir/src/manager/Manager.cpp.o
[ 33%] Building CXX object CMakeFiles/xrt.dir/src/tar…
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vivado.py function _read_compile_order() used by add_vivado_ip() fails with assertion when compile_order.txt contains references to files that are not VHDL or Verilog. However, some Vivado IP include …
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Hi
I tried to simulate few axi benchs using xilinx vivado simulator.
I could parse all the code with xvlog succesfuly
But during elaboration I get errors like:
```
$ xelab tb_axi_dw_downsizer
…
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Using latest Git main.
I tried to create a small unit test, but I was not able to repeat the issue with simple code.
https://github.com/jeras/verilator/commit/abba4830bc616cf71dde0ab2b82235cd6d0d0…
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Thank you for creating this project!
As the title says, I noticed the type mismatch errors below, which are also reported when assigning to variables instead of signals. It looks like `t_id0` and `…
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Hi,
I am reading your book and I am trying to run simulation on Vivado 2022.1 for CH1's logic_ex example. However, it fails on checking and show "FAIL: AND Gate mismatch". I tried to set Project de…
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Hi,
I am trying to simulate the eth_mac_10g_fifo_32 module using the provided testbench. But getting this error . I have tried to find out what the problem is but could not get anything.
Here is the…
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Running the attached Verilog testbench results in iverilog hanging. The curious thing is that hitting control-C to break the simulation, then continuing it sometimes (non-deterministically) results in…
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```
object ... {
def main(args: Array[String]): Unit = {
...
val compiled = SimConfig.withWave
.withXSim
.withXSimSourcesPaths(ArrayBuffer("..."),ArrayBuffer(""))
…