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Hello!
This is not a bug report for this project, rather a question regarding the Atmel fitters which you might have some input on since you probably have been using them a lot more that I have.
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Hi Brad,
I was playing around with macros in Vivado (specifically, how you specify the placement of the internal cells of a macro), which lead me to your read_tcp function. I have tried using this fu…
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### Version
Yosys 0.27 (git sha1 5f88c218b58, gcc 9.3.0 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
```verilog
// test.v
module test(output out0, out1);
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I am using sdn.parse() for parsing yosys edf outputs. Lots of circuits might have case sensitive wire names like 'n4139' and 'N4139'. In these cases, sdn.parse() merges these wires together which is w…
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We should do a literature survey to find possibly related work, we can collect the list of papers here and include notes/summaries from reading them
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### Version
Yosys 0.33+34
### On which OS did this happen?
Linux
### Reproduction Steps
Below Write first RTL RAM is written using blocking assignments synthesized as write first RAM.
**Yosys.ys…
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We think @arya1080 forgot to commit the updated Qsys files; error log below:
Error (12006): Node instance "dac_gain" instantiates undefined entity "qsys_system_dac_gain". Make sure that the requir…
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There are a lot of files used for examples. It would be nice to create a simple table in a markdown file in the same directory that gives the name, a short description of what the example does, and th…
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| name |about |title | labels | assignees|
|---|---|---|---|---|
| Iterative data processing | Description of the iterative processes in the use case. |Diversity of imput data | - |- |
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## Steps to reproduce the issue
I'm trying to synthesize the [VTR benchmark](https://github.com/verilog-to-routing/vtr-verilog-to-routing/tree/master/vtr_flow/benchmarks/verilog). I've added all mi…