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It is hard to get good feedback, so here are my comments.
A description of why this design is better than other designs would be helpful.
The image is great, but it took a while to understand …
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The AMDC hardware supports two encoder ports, but the FPGA has been configured for 1.
In the block diagram, the inputs are all going to one encoder block, with the second set being labeled as "alar…
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I'm trying to sketch out the work here before I go on leave. I think most of the work here will be plumbing into blocks we've already written, but there will be other little things that will need to b…
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Hi,
I've been trying to get this library to work on an Ice40 FPGA with Icestorm,
it -really- doesn't want to work thanks to the ' or posedge i_SPI_CS_n' of line 154.
On removal, it will compile…
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UTD Capstone
As we discussed today, here is your second option.
Problem: Writing our analog waveforms to our tasks on NI cards, which we must do when we change channels, is currently rate-limit…
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https://wiki.sipeed.com/hardware/zh/tang/tang-PMOD/FPGA_PMOD.html
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The Rasp Pi Zero 2 Quad Core V2.2 software provides faster ECG and IMU sampling and a more sophisticated core management strategy. While infrequent (once every 12 hours or so), the design has exhibit…
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Mr. BatchDrake
I am a hardware engineer, focus on fpga development.
could you please guide me on how to interface fpga stream to SigDigger. thanks.
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After merging https://github.com/bittide/bittide-hardware/pull/424 we're stuck with a pretty TODO in our code base:
```haskell
-- TODO: We used to perform a HITL test where the CPU would write…
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_From @mithro on July 17, 2015 7:30_
The FX2 should be loadable with firmware which makes it appear like a CDC-ACM serial port and is connected to the FPGA.
The FX2 has its two hardware UARTs connec…