nandland spi-slave issues - Githubissues

nandland / spi-slave

SPI Slave for FPGA in Verilog and VHDL

MIT License

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issues

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A method of detecting when the slave finished serializing a bit on MISO should be added.

#13 OmarAmer01 opened 6 months ago
0
CPHA fixed

#12 Buck008 opened 6 months ago
0
SPI_MODE/CPHA incorrectly implemented

#11 zzattack opened 2 years ago
3
Implicit latch for net r_SPI_MISO_Bit

#10 zzattack opened 2 years ago
0
Will the VHDL version be added?

#9 dsb298 opened 2 years ago
0
Update SPI_Slave.v

#8 motaz007 closed 2 years ago
0
Very minor spelling correction

#7 spez1998 closed 2 years ago
0
Fixed some (3) errors

#6 LeSpirou opened 4 years ago
0
w_CPOL assigned a value but never read

#5 HolyPriestFPGA opened 4 years ago
0
Corrected typos

#4 willz1200 closed 2 years ago
0
Warning: Async reset value `\r_TX_Byte [7]' is not constant!

#3 TCWilliamson opened 4 years ago
1
Fix typo

#2 pbsds closed 2 years ago
0
Add missing begin token, document the active low input pins

#1 pbsds closed 2 years ago
0