-
Hi,
I'm trying to generate an SoC with Chipyard and then pass the design to OpenLane for automated RTL-to-GDS.
I'm running the simulation for the example RocketConfig and then attempting to use …
-
(Note that I program in SystemVerilog, not VHDL)
Hello,
I'm trying to simulate your 'ym2149_audio.vhd' in ModelSim. Your core appear to properly receive my command and the PCM out does change …
-
Cocotb seems to have very limited support for SVA at this point. If I create an assertion:
```
ERROR_condition:
assert property (@(posedge clk)
condition
);
```
The simulat…
-
With reference to:
https://github.com/svunit/svunit/blob/84b88033590a1469a238be84d8526b25a9f29d10/bin/runSVUnit#L220C1-L220C96
`xelab` has a tendency to fail quietly when debug is not enabled (m…
-
Hi @MikeOpenHWGroup & @davideschiavone
A new CVFPU [PR](https://github.com/openhwgroup/cvfpu/pull/127) related to implementation tools has been opened.
Even if Synopsys Design Compiler didn't com…
-
### Is there an existing CVA6 bug for this?
- [x] I have searched the existing bug issues
### Bug Description
I am trying to synthesize the CVA6 core using open-source tools. Our synthesis flow inv…
-
I am attempting to use Verilator 5.015 for RTL simulation, and I've run into issues related to Verilator's support for SystemVerilog Assertions (SVA).
**Issues Faced**:
1. Verilator does not su…
-
yield statements seem like wait or join in Verilog.
I would like for Cocotb has more functionalities for event-waiting.
Systemverilog has three different kinds of join keywords, join, join_any, and j…
-
What I am asking for is some details on how to use system bus backpressure signals, so I can integrate quark into my FPGA synthesis and Verilator simulation (ISA tests). I will get through anyway but …
jeras updated
2 years ago
-
Is SystemVerilog support planned in Digital?
Thanks