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## summary
I met test faild when running test whith is combined with nngen 1.3.3 and veriloggen 2.1.0.
The test is matrix_add_use_map_ram.
I think the cause of that is purged MultibankRAM.disable…
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## summary
I met test faild when running test whith is combined with nngen 1.3.3 and veriloggen 2.1.0.
The test is test_matrix_max_pool_int16_ksize7_stride7_global_par2.py
### error message
…
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## summary
I met test faild when running test whith is combined with nngen 1.3.3 and veriloggen 2.1.0.
The test is test_matrix_avg_pool_int16_ksize7_stride7_global.py
### error message
`…
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I have followed the steps described in README to run the hello example.
When trying to synthesize the generated Verilog design with my synthesis tool it interrupts with an error message, complaining …
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I think veriloggen does not support SV interfaces at the moment?
Are these on the pipeline? It should not be too much of an update to add suport for them given the syntax and structure is pretty s…
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Traceback (most recent call last):
File "./RestructureNetlistSkywater.py", line 1033, in
main()
File "./RestructureNetlistSkywater.py", line 169, in main
m = from_verilog.read_verilog…
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Hi, is there any example about how to get some combinational block? grepping on the examples I found something but it all is related to the test and not the generated RTL I believe?
```
veriloggen…
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Dear Mr./ Ms.
I found this program useful, but have one thing wish to confirm.
Is Pyverilog a program that allow me to input python code and execute in verilog?
As I am planning to design an AI…
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I think Indirect access RAM can be realized based on stream.LUT.
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I'm requesting to support AXI Stream interface in veriloggen. It might be useful to design stream architecture.