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All,
Because the current test bench is too simple for me to learn the sweRV, thus I use FreeRTOS as the target to learn how to control this great design. With small modification of original test benc…
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Author Name: **Todd Strader** (@toddstrader)
Original Redmine Issue: 1547 from https://www.veripool.org
Original Assignee: Todd Strader (@toddstrader)
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Currently, for verilator CI we are c…
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Hello,I am a student. When I used it to test my use cases, the results were not consistent with my expectations.
the problem of my testcase is
#13923 0 00000000800002c8 800000b7 r 0000000000000001 …
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Author Name: **Todd Strader** (@toddstrader)
Original Redmine Issue: 1483 from https://www.veripool.org
Original Assignee: Todd Strader (@toddstrader)
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This is still a WIP, but I think it …
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Hello
I compile SweRVolf in Ubuntu 16.04, Verilator 4.010 and get a compilation error. I guess this is due to using an incompatible Verilator version
> /usr/local/verilator/4.010/bin/verilator -…
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The CI catches these, but would be good if we can have that beforehand.
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I'm running SymbiYosys on https://github.com/ispras/hdl-benchmarks/blob/master/verilog/texas97/PI_BUS/multi_master/bus.v module. This module uses several defines from https://github.com/ispras/hdl-ben…
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Is there way to generate tests in any other directory than riscv-dv?
We usually don't run in repository. We run randoms in separate working area which is cleaned periodically.
the generator file…
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What is the difference between https://github.com/chipsalliance/Cores-SweRV and https://github.com/westerndigitalcorporation/swerv_eh1. Are they maintained by the same people?
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In section 3.12.23 of "RISC-V External Debug Support Version 0.13.2", write "sbdata0" operation will trigger the system bus write access operation. But in dbg.sv, the write or read access operation is…