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I have a hierarchical design in Sky130 where Magic is flagging DRC errors for the block-level GDS, but not the top-level that integrates that GDS with a padring. I'm curious why this might be the case…
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#### Description
It's not allowed to create subinterface on a interface that is assigned to vlan.
#### Steps to reproduce the issue:
1. config add vlan 100
2. config vlan member add -u 100 Eth…
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Hi, thanks for the good work!
Maybe I missed something, but I couldn't find an example of how to initialize a register value:
```veryl
pub module RegisterFile (
i_clk: input clock,
) {
v…
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WDYT? Is this publication in scope?
```
@inbook{Valencia_2019,
author = {Valencia, Felipe and Polian, Ilia and Regazzoni, Francesco},
booktitle = {Embedded Computer Systems: Architectures, Modeling,…
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@HardhatChad I admire the design goal of thwarting ASICs so we can have PoW without obscene energy consumption. However, if that's the objective, then I would strongly advise against taking the "rando…
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While going through the X-HEEP ASIC flow I can't seem to run the openroad-sky130 target and get GDS out.
I have OpenROAD installed globally on my machine, oss cad suite and I've ran the installation…
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I'm using Verilator as part of a software for teaching digital design with the help of SystemVerilog, and we expect our students to not use any kind of inline logic net initialization. Shown in the e…
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Description:
Original issue (https://github.com/Azure/sonic-sairedis/issues/899) addressed the problem in the comparison logic.
However, the root cause seems to be in OA 'temp' view construction log…
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What is the estimated speedup of the design as an ASIC, given smaller feature sizes and hence higher clock speeds? Could this possibly be 10x?
Further, I notice that the number of clk/sq for pearso…