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I have a hierarchical design in Sky130 where Magic is flagging DRC errors for the block-level GDS, but not the top-level that integrates that GDS with a padring. I'm curious why this might be the case…
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https://github.com/SChernykh/CryptonightR/issues/1#issuecomment-452775046
> In fact, a carefully designed ASIC could still outperform GPU by spending more resource/area on the bottlenecks. The memo…
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Two categories of possible errors have been checked at the time the mapping Excel docs were finalized:
- **Errors due to pin-assigning in the process of mapping each net/connection:**
1. Check tha…
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### Link to Internship Posting
https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/NVIDIA-2025-Internships--Hardware-ASIC-Design-_JR1986523
### Company Name
NV…
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The undocumented [ED 71], albeit commonly called `out (c),0`, can actually output a value different than zero depending on the implementation - for instance on the SEGA Game Gear (CMOS) it outputs `0x…
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What is the estimated speedup of the design as an ASIC, given smaller feature sizes and hence higher clock speeds? Could this possibly be 10x?
Further, I notice that the number of clk/sq for pearso…
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This is one of the rarest packages I came across in context of ASIC design flow within the julia ecosystem :)
I would be happy to contribute and work on this package and one starting point I can th…
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Description:
Original issue (https://github.com/Azure/sonic-sairedis/issues/899) addressed the problem in the comparison logic.
However, the root cause seems to be in OA 'temp' view construction log…
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It would be great to have an example project on how to use bazel_rules_hdl for OpenROAD and asap7.