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Hi. I find there is also something wrong with multi-dimensional fixed size vector. The simulation in forsyde deep is fine, but the generated VHDL code cannot be simulated.
My code is:
```
{-# …
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In vanilla Bash, pressing TAB prints the completion candidates and then the prompt:
```
he /home/waldo # ls
.altera.quartus/ .dmypy.json .mypy_ca…
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Hi Seb,
Thanks for all the great work you've done. I'm wondering about the device tree source file that you've written. The FPGA configuration that I'm using will not enable some of the peripheral…
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I have an issue when running multiple threads using the Questa simulator and the flag `-p`. I created a minimal example to reproduce the issue.
The testbench implements a single test case:
```vhd
…
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I just imported a quartus project into TerosHDL, and I can't manage to compile it with TerosHDL, although it works from Quartus.
I get the following error:
```
Info: Elaborating from top-level …
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Hello,
I tried to setup PoC as described in the Quickstart Guide in the readme. After experiencing the bug described in #62 and applying the suggested fix (renaming PoC.py in the submodule) the fol…
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OS: Ubuntu Mate 21.10 64bits
System: Raspberry Pi 4B 4GB
#Overclock options:
over_voltage=2
arm_freq=1750
gpu_freq=600
gpu_mem=256
BOX version: compiled from box64-0.1.6 source
Trying to …
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# Summary
I tried to run the vector_add example under DirectProgramming/C++SYCL. The emulation runs well and the simulation can be compiled successfully. However, the simulation failed to run.
# …
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I have followed to https://github.com/SpinalHDL/VexRiscv/tree/master/doc/nativeJtag, but I need to modify for my Altera DE0-Nano-SoC board (Cyclone® V SE 5CSEMA4U23C6N device) and Altera Virtual JTAG.…
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I run
```
cascade --march de10 -e share/cascade/test/benchmark/bitcoin/run_25.v --enable_info --profile 3
```
but it runs on CPU.
In ```De10Compiler::compile``` ```De10Compiler::block_on_compile…