-
**Description**
When using the GHDL plugin to yosys, and probably more generally, attributes are not attached to instantiations. This causes (for example) yosys to optimise away instantiated blocks …
-
Xyce/ADMS recognises three display system tasks:
`$strobe` displays when the simulator has converged on a solution for all nodes;
`$display` provides the same capabilities as `$strobe`;
`$write` …
-
`yosys> plugin -i systemverilog
ERROR: Can't load module `./systemverilog': /usr/bin/../share/yosys/plugins/systemverilog.so: undefined symbol: _ZN5Yosys4Pass11on_registerEv`
ubuntu 20.04 LTS in W…
-
`invalid-system-task-function` states:
> Checks that no forbidden system tasks or functions are used. These consist of the following functions: `$psprintf`, `$random`, and `$dist_*`. As well as non-L…
-
Hello.
hdlConvertor does not support the parallel_case attribute. An example can be found here: https://github.com/KatCe/hdlConvertor_issue_185
Using the python script in the repo I tried all 3…
KatCe updated
10 months ago
-
TerosHDL:Global output: 2024-06-19 09:53:02.780 [info] [00000.001204] ERROR: Can't guess frontend for input file `d:/workSpace/sim/fifo/axis_async_fifo.v;' (missing -f option)!
When I'm in the CMD wi…
-
`VerilogTranslationPass` fail with the following example.
```
def mk_aType(a: int = 4, b: int = 6):
return mk_bitstruct(
"aType",
{
"a": mk_bits(a),
…
-
Opening Settings -> Editor -> Code style -> System Verilog hangs forever. This means you can't edit the coding style at the moment.
igmar updated
5 years ago
-
Hi Vitor,
Many thanks for your excellent work on this plugin! I was trying it, and saw that sv structs and class still can't do autocompletion. I saw issue #150 is still open and got to wonder if t…
-
Hi @MarcoIeni,
I was running VUnit using this repository as a base, combined with github actions and simple but different source code.
The simulated verification fails to compile with the code …