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Hi! I really like the project and would see a ton of use for it in our FPGA/ASIC projects. However, one blocker I see is the lack of parameters on the HDL modules generated. I often have multiple inst…
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add a Select all to make linking documents faster
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# Description
The script for running the Verilog conversion and the convert.py is fixed and is the `tests/verilog-conversion/run-compare.py`.
However, convert.py requires changes to correctly conv…
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## Issue Description
Getting following error
```
../../tests/dff_udp1.v line 11 - ERROR: syntax error, unexpected CLOSE_BRACKET
- ')'
- Parse failed
```
File ../../tests/dff_udp1.v obta…
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Hello,
I want to use HDL AST to generate **Verilog (not System Verilog)**, but I am **worried that whether the converted file will have System Verilog specific syntax**. I see the class name in the …
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**Is your feature request related to a problem? Please describe.**
In the CircuirtVerse we have only a Module export to the Verilog description language.
**Describe the solution you'd like**
The …
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https://josh-gao.top/posts/ecb88422.html
Verilog HDL 的基本功能之一是描述可综合的硬件电路。如何合理使用 Verilog HDL 描述高性能的可综合电路是 Verilog 系列学习笔记的目的，也是后续要讨论的主要问题。 本文介绍了 RTL 和综合的基本概念，通过常用 RTL 电路模型来对可综合的 RTL 级描述方式建立整体性的认识。力图通过…
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I have been using cocotb for a while and decided to switch to the Python runner approach instead of using a Makefile.
The problem that I found is that, when I use Xcelium as a simulator and open th…
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With the `sequence.hdl` example, the `_FSM` variable in the generated Verilog is never declared, so it defaults to a 1-bit `wire`. This results in it toggling between two states instead of going throu…
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Our first development plan went great. On to the next!
These are the issues that were either left out unfinished in #25, requested by people or bugs
1. Auto Alignment (Format Document/Selection) -…