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Hi @Dolu1990,
I'm currently in the process of bringing up the JTAG interface on the VexRiscv silicon. After I switched the TDO and TDI signals I got the following error:
```
Open On-Chip Debugger…
dnltz updated
2 years ago
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I can not upload Sketchs to the Micro:bit v2 from a Macbook Air M1. It keeps saying the following error messsage:
Error: No Valid JTAG Interface Configured.
Arduino: 1.8.19 (Mac OS X), Board: …
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What adapter & software did you use for JTAGing the AP320?
I think I may be able to scrounge up something from my parts bin to use as a JTAG but I'm a little rusty :>
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I have followed to https://github.com/SpinalHDL/VexRiscv/tree/master/doc/nativeJtag, but I need to modify for my Altera DE0-Nano-SoC board (Cyclone® V SE 5CSEMA4U23C6N device) and Altera Virtual JTAG.…
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Hi,
I have a Nexys A7, the successor of the Nexys4DDR (according to the manufacturer, the boards are almost the same).
I installed Vivado 2018.2, took the 1.5 SweRV core, changed the strings ask…
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Hello,
I understand that Arty A7 is supported, I want to confirm if Arty S7 need something extra to work.
I follow the build instructions and when loading the gateware on Arty S7 I am getting the …
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```
Prerequisite '../cube/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc/startup_stm32f030xc.s' is older than target '../bin/main.elf'.
No need to remake target '../bin/main.elf'.
Fini…
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Hi Olof,
I'm new in FPGAs and wondering how does your bscan_tap module work ? where are the definitions / descriptions of the BSCAN2 modules? How are some internal wires driven?
Thanks in advanc…
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## Issue Description
Issue discovered in https://github.com/openXC7/nextpnr-xilinx/issues/20#issuecomment-1942858331
When IS_WCLK_INVERTED property is asserted, we expect the write to LUTRAM to …
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Currently I am developing against a local SpinalHDL `dev` branch, along with local VexRiscv `dev` and the VexRiscv-specific latest OpenOCD (i.e. using the "old" VexRiscv debug module") and I am seeing…