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### Issue
The generator outputs `modify_instruction.v` which contains the following lines:
```
output reg [31:0] qed_instruction;
...
assign qed_instruction = ...;
```
In QuestaSim vlog compi…
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Dear tangxifan,
I have used this folder: openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff to run openfpga. Preconfigured testbench runs and give expected results. However, within same task I …
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hi i am student and dont have questasim and xcelium. I am also not able to find any student editions available online. Does anyone know any free alternatives for simuation or know if questa intel wou…
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I am new to the makefile stuff.I decided to check some examples before creating my own make file. So I downloaded this project.
But when I CD to the folder and ran make command, only the echo messages…
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I am trying to execute ``` fmatmul ``` program in Ideal Dispatcher mode.
The steps i have taken is :
1.
```
cd apps
make bin/fmatmul.ideal
```
and the output got is :
```
cd fmatmul && i…
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vlib: Command not found.
vlib: Command not found.
--> Compiling PULPino Platform...
--> Compiling PULP IPs libraries...
--> Compiling axi_node...
vlib: Command not found.
vmap: Command not…
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
Instruction retire counters `minstret` and `minstreth` are incremented and updated (wri…
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Hello,
When I try to compile UVVM with questasim 2019.1, I always run into this compile_all.do script returning with an error.
```
# eval vcom -quiet -suppress 1346,1236,1090 -2008 -work uvvm_util…
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On verilator, SV structs are shown as `ModifiableObject`. Because of this it shows up a single dimensional packed vector, and we can't access the struct fields separately. On questasim, they are show…
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According to SystemVerilog spec, the example code below with typed constructor call (` c = D::new()`) is legal syntax. Which is supported by QuestaSim 2021.2
class C;
virtual function …