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This is related to the testing part of issue #128. I have written a Python script that tries to import all the defined `Platform` classes in nmigen-boards and then checks if building blinky using the …
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I have a repository with cores generated in ISE 14.7. Unfortunately, the stub files are not present so I'm unable to use XilinxCoreLib and I have to use the `.edn` netlists. ActiveHDL (and ModelSim I …
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_From @mithro on July 14, 2014 12:8_
The Xilinx Zynq-7000 series devices are a combined ARM processor with a "series 7" FPGA. The [Digilent ZYBO](http://www.digilentinc.com/Products/Detail.cfm?NavPat…
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Apparently, the proper way to constrain some CDCs (Both AsyncResetSynchronizer and transfer via GreyCounters) should use a max_delay constraint and not a false path.
https://forums.xilinx.com/t5/Vi…
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INSTALL.md:
Getting the dependencies to build the firmware (arm-none-eabi-gcc, arm-none-eabi-newlib) and not documented when targeting Pano G1. Listing the version tested with, and the source would…
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# [prjxray] Apply prjxray ideas to document the bitstream for Spartan 6 parts
# Brief explanation
Spartan 6 is a hugely popular part which would be awesome to have support for in SymbiFlow
##…
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openFPGAloader built from fresh git.
FPGA: Xilinx xc6slx150tcsg484
Flash chip: M25P128-VME6GB
SPI wires: 1
Flashing from Xilinx Impact works without a problem (using generated .mcs file).
I…
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Using the latest master branch it doesn't seem to be possible to build the gateware for any ISE based Board. The process fails with the error message:
```Writing file top_map.ngm...
Running directed…
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![PXL_20220614_003347449.jpg](https://user-images.githubusercontent.com/19699320/173469323-be35b41f-29b2-4e68-abbe-4730698d45ff.jpg)
I've got this FPGA board that I wish to support. It's got multiple…
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How did you configure the toolchain? If act on the guide from the riscv site, then there is no support for the flags -m32 and -msoft-float.