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Hello,
I just want to thank you for developing this controller and open sourcing it! It must have been a huge undertaking.
I'm trying to use you controller in a project of mine that is targeting a N…
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https://github.com/antmicro/distant-bes
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I am trying to reproduce the NaxRiscv/Debian setup as described [here](https://spinalhdl.github.io/NaxRiscv-Rtd/main/NaxRiscv/hardware/index.html) and am running into some issues.
Steps I have unte…
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Hey, I want to build litex project with ethernet peripheral. I succesfully builded project and generated bit file. I'm trying to loading boot.json file but I got this error.
![image](https://github.…
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Hello enjoy-digital,
I've tried to integrate a simple SoC to test serwb like below:
First, defined serwb memory map:
```python
mem_map = {**soc_cls.mem_map, **{
"ethmac": 0xb00000…
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Hi,
I'm trying to build and to use this repo with an lambdaconcept ECPIX5 and observe some issues:
- litex: `linuxq` must be replaced by `linux`, `linux4` by `linux --cpu-num-cores 4`
- busybox: `C…
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Hi there,
i stumbled upon a severe timing issue with Liteeth while trying to bring up a quad core Naxriscv SoC on the Nexys Video.
In the generated xdc there is:
```
create_clock -name eth_clo…
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I have run into an issue when booting from an SD card. I am using a nexys video board. On commit 2059e65, Linux boots correctly when using a Gigastone SD card, but I get the error below when using a S…
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While building bitstream for nexys video with configuartion of rocket64b1 the following errror has been observed
``Exception: sbt.TrapExitSecurityException thrown from the UncaughtExceptionHandler in…
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Hi,dear dolu,
I am currently learning how to use the kernel generated by Litex to run the dhrystone algorithm on SOC. The specific operation is: 1. Generate a SOC system with a Nax core, and then bas…