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I want to run ONNX Model On Spike: Inference
I clone the code
`https://github.com/ucb-bar/onnxruntime-riscv.git`
then
`git submodule update --init --recursive`
`./scripts/build-onnx-inference.s…
GGKOP updated
5 months ago
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While debugging a SoC with a 64-bit RISC-V processor and a Debug Module (Spec 1.00), we're encountering connectivity issues with OpenOCD. The error indicates a failure to read the MISA register, sugge…
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```
+ cd build/linux-riscv64-normal-server-release/hotspot/linux_riscv_compiler2/generated
+ bash -c '/usr/bin/g++ -DLINUX -D_GNU_SOURCE -DRISCV64 -DPRODUCT -I. -I/home/yansendao/git/riscv-port-jdk8…
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HI
we are trying to run cv32e40x
corev_rand_arithmetic_base_test , but we are facing the error.
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I implemented SweRV_EH1 on a Zedboard fpga. I am trying to use openOCD and Jtag Arm-USB-Tiny_H to download code to the board as instructed in the README. I have checked the physical connection and ma…
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
A couple of years ago, CVA6 did manage to successfully run the PMP benchmark. The PMP b…
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```
+ cd build/linux-riscv64-normal-server-release/hotspot/linux_riscv_compiler2/generated
+ bash -c '/usr/bin/g++ -DLINUX -D_GNU_SOURCE -DRISCV64 -DASSERT -DCHECK_UNHANDLED_OOPS -I. -I/home/yansend…
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Hello @enjoy-digital,
I wanted to utilize the risc-v debug module provided in `core.py` within `litex/litex/soc/cores/cpu/cv32e40p` https://github.com/enjoy-digital/litex/blob/76a704377fbd2897a5ab…
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Demo repo: https://github.com/dreiss/panic_repro . It's a fairly simple riscv-rt example targeting riscv64 on qemu.
On "rustc 1.78.0-nightly (a84bb95a1 2024-02-13)" or later, the link fails with b…
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Cloned the `riscof` framework via the command which went smoothly:
```zsh
pip3 install git+https://github.com/riscv/riscof.git
```
However, running `riscof` via the command:
```zsh
riscof --ve…