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I am trying to build FemtoRV petitbateu but it fails to build two different ways for two different toolchains.
When I build with yosys+nextpnr using command: `python3 -m litex_boards.targets.digile…
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### Summary
We've observed that Fastino occasionally fails to initialise properly on power-up.
Our suspicion is that the bitstream is not being read correctly because the power-up sequencing fo…
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Hi all, our lab has only a soc xilinx zcu102 and i'm a freshman of FPGA developing. I want to verify zynqnet on zcu102 so i have to transplant it from 7045 to zcu102. Are there any docs or other proje…
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# Tutorial for SymbiFlow with Buildroot Linux on RISC-V
# Brief explanation
Write a tutorial for getting started with SymbiFlow on a Linux-enabled RISC-V CPU on a mid-range FPGA with Buildroot L…
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Hello Howard,
Many thanks for your Cyclone 5 tutorials they have been a great help.
I have been looking at your interrupt example and have successfully run it on the Arrow Sockit board. However I am…
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Hello @bl0x,
First off let me thank you for your project. It is interesting and I am going to try and follow it to gain an understanding of amaranth.
I am trying to build with Vivado and have h…
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Good day,
I have Sipeed Tang Nano 1K (which is replacement for Tang Nano already supported in Litex) with GW1NZ-LV1QN48C6/I5 and BL702 usb-jtag
Here's its documentation https://wiki.sipeed.com/h…
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Hi,
I have been trying to do the SoC example for the Arty A7 and I had a problem when it is the time to add the .bram_tcm file. My doubt is how it is possible to attach the software file in the sy…
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Hello, I have encountered some issues regarding FPGA synthesis. I conducted a comprehensive analysis of the entire ARA and found that it would terminate abnormally, and reported an abnormal terminati…