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Hi
what's the roadmap of the features and any site about the throughput data?
Thanks
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**Which problem is this feature request solving?**
Instance, net, and reg in the VSCode outline use the same icons, making them difficult to distinguish.
This forces me to look at the small prin…
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## System information
```
MyHDL Version: 0.12: experimental work on new converter
Python Version: 3.10+
```
I am working on a new converter approach to accommodate future target languages (first …
josyb updated
2 months ago
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In the Makefile, I see there is the `riscv.smt_model` target, I was hoping it can generate models in SMT-LIB2 format (is that what it means to be?), but it seems that does not work for me.
The erro…
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I tried running `make -f Makefile.himbaechel` in the `/examples/himbaechel/` directory, which produced the following error at the end. Any suggestions on this? I'm running this on MacOS with qt5 insta…
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Verilator Overview [Reference](https://colab.research.google.com/github/byuccl/digital_design_colab/blob/master/Tutorials/verilator_overview/verilator_overview.ipynb) and Verilog with VS Code [Referen…
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### Motivation
I'm wondering if we can have a helper function to save system Verilog module `generateSynth()` to a file. Its a pain to keep copy pasting the code below to keep track of system verilog…
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#### Expected Behaviour
VPR should be successful
#### Current Behaviour
When I use the arch in [https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/arch/COFFE_22…
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Hi,
I want to restrict my application to only verilog programs and not system verilog, can you help me figure out the grammar specification for only .v files?
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Hi I have a highliting issue on a system-verilog file while using tree-sitter on neovim.
These are my system-verilog lines of code:
![image](https://user-images.githubusercontent.com/50401154/21534…