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I have purchased 5 of the QMTech boards for work purposes (arriving later this week), so should be able to use one to experiment with the open source flow. I also have (limited) access to the Genesy…
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I have compiled openFPGAloader with pamac (I use Manjaro). When I try to flash my Tang Nano 4k, I get:
```
sudo openFPGALoader -b tangnano4k -f '/home/chandler/GoWin Educational IDE/IDE/bin/hello_…
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Done synthesis with yosys+nextpnr on a Xilinx Artix-7 FPGA (no vivado, no symbiflow).
Tested with a FemtoRV CPU at 50MHz. It still requires manual removal of unised FD primitives intances in the gene…
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I want to compile the FPGA source, but I can not open the project in Xilinx Vivado?
how can open and build an FPGA source in GUI mode? It is the way I open it like a normal FPGA project...
thanks …
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Hi,
I have detected two errors with STEP and Render 3D.
Installed on Fedora 35 and version [4b0f7a2].
Step export enable, Log with kibot -v:
-------------------------------------------------…
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- [x] arrange that all designators and texts do no overlap, make sure they are not inverted (I know about Altium option)
- [x] please add 0R option resistor that grounds input connectors
- [x] add …
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At first I must say your open-source FPU is really helpful for me, and I learn lots of knowledge about how to design FPU from it.
I find that in ```fpnew_pipe_out.sv``` you just add some registers …
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I was [comparing Yosys against ISE and Vivado](https://github.com/rodrigomelo9/yosys-versus), using examples provided by Xilinx. I want to remarks that from 178 examples, only 12 failed using Yosys + …
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Some HTML sections like BRAM have changed after recent commits (think they are broken?). Review after BRAM DB commits to get them into a reasonable state
This will probably start a larger conversat…
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OS: Windows 10
Note: Building in a OneDrive synced directory.
Logs:
```bash
C:\Users\\OneDrive - Microsoft\Documents\bugbash\iot-middleware-freertos-samples>cmake -G Ninja -DVENDOR=ST -DBOARD=b-…