-
Hello everyone,
I am interested in creating a SoC with 2 cores and a custom communication between them (UART or something else). But reading the BaseSoC implementation, I see no trick that I could …
-
With booting Linux on rocket, i get the following error:
```
[ 0.078624] chip_bus_sync_unlock: irq_bus_sync_unlock not set for irq 11
[ 0.078691] desc->handle_irq: ffffffff8032c36c (null)
…
-
I'm currently trying to bring up a 8.2 board, and I can only find a working seed by reducing the sysclock to 40Mhz - apparently much older versions of litex/this repo (pre 32 bit eth data path) were a…
-
While using command `litex_sim --cpu-type=vexriscv` I have folling error:
```
/home/wojtess/programs/litex/litex/litex/build/sim/core/modules/xgmii_ethernet/xgmii_ethernet.c:11:10: fatal error: json…
-
Both Vivado sim and icarus are unable get past time 0. I get the following error in vivado
**FATAL_ERROR: Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation t…
-
Reported by @AndrewD, to look at this:
- Run NuttX with LiteEth on a board with `add_ethernet `.
- Run NuttX with LiteEth on a board with `add_etherbone + hybrid mode`.
- If issue with the latter,…
-
### Version
Yosys 0.39+124 (git sha1 d73f71e813d, g++ 12.2.0 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
I was very surprised to see an extremely high logi…
-
Hi charles,
How will it be possible to run linux on Litex-Naxriscv like as https://github.com/litex-hub/linux-on-litex-vexriscv
I like to run (NaxRISCV 64 bit ) RISCV 64 Debian Linux on FPGA…
-
Hi,
As a suggestion, the python's requirement should be updated to Python v3.7+
I tried to run `litex_sim` with following arguments:
`litex_sim --with-sdram --no-compile-gateware -cpu-type=cv32…
-
The verilog was generated from https://github.com/rowanG077/liteeth-16-byte-bug/tree/testing
with the commands:
```
./colorlite.py --ip-address=10.0.11.43 --build
./sim.sh
```
Ignore the `…