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On `master`, using GHC 9.6.2, I'm seeing:
```
$ cabal run clash-testsuite -- --no-vivado -p IntegralTB.SystemVerilog
Warning: Requested index-state 2023-06-17T22:28:17Z is newer than
'head.hacka…
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Currently, Yosys requires specifying each file individually in the command line or script for synthesis or formal analysis. This can be cumbersome for large projects with many files. I propose the add…
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I would like to have a Python method, which exports all dependencies for a given source file into a format, which common IDE's accept.
I'm using vivado, which can read a .tcl file. So the method s…
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For testing with netlists I need some vendor libraries. These are shipped with the simulator ActiveHDL and I use this to include them
```
vu.add_external_library('pmi_work', activehdl_lattice_path /…
ghost updated
4 years ago
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Hi, I hope you are well.
Does Piccolo support FreeRTOS?
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We've been evaluating using VexRiscv for a project, and it's mostly been going beautifully. Even though nobody on our team knows Scala super well, VexRiscv and SpinalHDL so far is a hit because of how…
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Hi, I am working on the hello world test of "lowrisc-chip". The branch that I am working on is kc705_update. The problem is that I can generate the bitstream file and combine it with the "hello world"…
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With respect to the following comments:
```
// Simulation problem
// Sometimes (like in MULM1) DBH is not set. AU is used in these cases just as a 6 bits counter testing if bits 5-0 are zero.
/…
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## Observed Behavior
I am getting the following error when running the tests using the default configuration (OpenTitan).
```
# UVM_FATAL ibex/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_co…
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Hi. I was hoping I could get some examples of fsva use, particularly using xsim/Vivado using some of the features listed on the ReadMe, such as OSVVM.
Also I was wondering if this tool could ouput …