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Hi,
I have a doubt about the following piece of code in `top.cpp`
```
// signals to be mapped to the AXI master port (hostmem)
#pragma HLS INTERFACE m_axi offset=slave port=in bundle=hostmem dept…
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I have followed the tutorial : https://red-pitaya-fpga-examples.readthedocs.io/en/latest/_downloads/StartprogrammingFPGAusingRedPitayaboard.pdf
And the result of my compilation is following (bit-st…
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Hi all,
I am experimenting with sending lw and sw signals for addresses residing in the IOSPACE (0x80000000 - 0x8fffffff) (untethered version v 0.2).
If I issue any command (lw or sw on its own…
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Hi guys
For a 2-core Rocket-based Linux system, I need to implement a non-cached non-paged Scatter-Gather DMA as a part of the ROCC module. My DMA should have a high-throughput low-latency access t…
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I am leveraging the axi_lite_xbar component to interface a hardware architecture processor to a variety of peripherals. As I am not terribly concerned with performance, I set it up to have two master…
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In branch "Add_hdl_helloworld"
There may have a bug around DMA logic.
### Reproduce the issue
Please select `Action Type (HDL Action - manually set ACTION_ROOT in snap_env.sh!)` in `make snap_co…
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For now, midas depends on rocketchip, so regardless of the target design, we should import rocketchip to use midas. This is very unacceptable in most cases including midas-examples. midas needs to dep…
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I want to run OTBR with some other containers (node-red) and cannot figure out how to configure IPv6 settings between them. I consider clean IPv6 network, regardless IPv4 support.
At docker host I cr…
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**Description**
I'm using an enhanced AXi4 Lite register entity, that was originally generated by Xilinx Vivado. Instead of using integer register indices, I'm using enumeration literals.
```vhdl
…
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`TbAxi4LIte_compile.txt` on branch `dev` references non existing files.
Please use an appropriate file extension.
The files is an ASCII encoded data base file and not text file.
**Suggestions…