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The attached example ([error-BLKANDNBLK.tar.gz](https://github.com/verilator/verilator/files/7695690/error-BLKANDNBLK.tar.gz)) gives this error:
```
%Error-BLKANDNBLK: mod.v:6:16: Unsupported: Block…
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### Describe the bug
In SystemVerilog, the `always_comb` sensitivities are only signals referenced within the `always_comb` block. In ROHD, currently, any combinational signal that may modify the in…
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cococtb: master (4aee0a0895a36606f9263df9370405663f496d22)
Ubuntu 20.04.2 LTS on WSL2
simulator: Verilator 5.007 devel rev v5.006-7-g4a8cfe367
---
When `pytest.raises()` fails, it raises a `…
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Hi there,
Thanks for taking time reading my issue.
I am trying to use CIRCT and Calyx to lower my MLIR which is a simple four-element vector addition.
I used the following lowering pipeline t…
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So the below code works OK:
```
static vpiHandle clk;
s_vpi_value val;
int a = 1;
val.format = vpiIntVal;
val.value.integer = a;
vpi_put_value(clk, &val, NULL, vpiNoDelay);
```
It d…
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Alright, got things upgraded and tried running it. It sort of works, but the connection seems unstable. This is what I get on a "good" run:
```
pi@betrusted-dev:~/code/betrusted-scri…
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Hello @nickg,
I was wondering about the approach you would like to take when approaching Mixed-language simulation with Verilog/System Verilog. I remember you mentioned that you would like to add s…
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Hi,
Thank you for updating the new version of openwifi-v1.4.0. Recently, I encountered some problems while build FPGA of openwifi-v1.4.0.I am experimenting with Ubuntu 2018.The version of VIVADO I us…
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Hi all, first of all thank you for writing this tool. It's a great idea and we would like to try it in our team. When using the following sim_arg `sim_args=['-L /home/edian/Applications/intelFPGA_lite…
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Hi!
I am currently working on reimplementing the rfuzz passes in yosys to make it compatible with some other tools I am working with. I have realised that the width of the coverage port does not ma…