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It seems this crate has the restriction that all modules always operate in the same clock domain.
Are there any plans to remove this restriction? :)
Btw, do you have a recommendation which crate o…
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### Description of the setup:
* Device: STEM Lab 125-14
* SD card image: Alpine 20220302
* Application: sdr-transceiver
* Development Machine:
* VirtualBox running on windows 10
…
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We get a GHDL failure in the release CI pipeline on master:
Log: https://github.com/cocotb/cocotb/actions/runs/3816250240/jobs/6491822293
```
nox > Running simulator-specific tests against a si…
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Hi, All
I found a command file is needed if you want setting a timescale with iverilog.
```bash
+timescale+1ns/10ps
```
I wonder if there is a easier way to set timescale in iveirlog, somethin…
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Hello,
my name is Lorenzo Lagostina, I'm working on a research project at the Polytechnic of Turin.
The research project is focused on back-end techniques, and we decided to apply them to…
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Hi,
I've finally managed to run compliance tests with riscof on our RTL model and got 16 passes and 74 fails.
diff for caddi-01 test has two extra zero values at the end of seil reference signat…
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I found this project after a deep dive into actor frameworks and I think it's great. I would love to contribute, but I'm not sure my low-level knowledge is enough for all the hard work. But I do have …
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Hi there,
Recently, I have build support for a CVA6 core for 4 bitmanip subgroups and wanted to test them for validity. Coming to this point, I have found out that there is not actually any student l…
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@rmanohar I will implement it but i wanted to get your ok/opinion first. also any wishes for the char that i use as flag?
**Describe the bug**
cadence xelium/spectre and for some parts innovus do…
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Currently, we have two ways of running Calyx-generated RTL:
* Simple hardware, open-source simulator: This is the "normal" way of running Calyx programs. We compile the core design to Verilog and u…