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I followed the [Getting Started](https://docs.calyxir.org/#getting-started) tutorial and was able to successfully install everything needed - running `fud check` tells me that everything besides `inte…
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# Description
The script for running the Verilog conversion and the convert.py is fixed and is the `tests/verilog-conversion/run-compare.py`.
However, convert.py requires changes to correctly conv…
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Hello,
How can I add an include path in a way that macros will be found using F12 ? I'm pretty new to vscode so I'm not sure this is a vscode or Verilog-HDL configuration.
For instance, I'm incl…
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vpr has the following options;
```
netlist options:
--absorb_buffer_luts {on, off}
Controls whether LUTS programmed as buffers are absorbed by
downstrea…
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I'm not sure exactly where on the wiki to start this conversation, but I'm here compiling a few links on LabVIEW FPGA compilation. It's a relatively mature ecosystem that National Instruments has crea…
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**Describe the bug**
verible-verilog-syntax accepts generate for-loops with the wrong index
**To Reproduce**
DUT, in file `test.sv`
```systemverilog
module add(input logic a, input logic …
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**Minimal test case**. [simbug.zip](https://github.com/nmigen/nmigen/files/5961206/simbug.zip)
**Summary:**
The Verilog that nMigen outputs can contain time-0 race conditions which cause problem…
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### Version
yosys 0.35+56
### On which OS did this happen?
Linux
### Reproduction Steps
Hello,
While engaging in the synthesis process with Yosys, I faced a challenge when read the design file (…
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For the verilog_mode, engineers at the company typically use it with gvim. However, the step of copying verilog-mode.el* to /usr/share/emacs/site-lisp requires administrative privileges, which many en…
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The EDAM format is missing the concept of Verilog compilation units. Comparing the implementation of the tools Modelsim and Vcs shows that Modelsim chooses to compile each file in its own compilation …