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Here is the sample example code from documentation:
```
module our (input clk);
reg readme /*verilator public_flat_rd*/;
initial $finish;
endmodule
```
If I use [standard attributes](https:…
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**Problem:**
* The current framework enforces a compilation order between VHDL and Verilog sources (e.g. in the case of the Questa simulator, all VHDL sources are compiled before Verilog). This can …
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Does not appear to repro when extracted as a separate function which just takes the parameters as arguments (rather than embedded in an array of pointers). Might be something to do with the JIT envir…
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Is it possible to declare a symbol as a primitive, but also to have a property with the name of a sym_name.v file found in one of the libraries which contains the verilog code for the symbol?
Similar…
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Below is a test case.
```
module test();
reg expected = 1;
initial begin
$display("Const Positive %s", 1 ? "yes" : "NO");
$display("Const Negative %s", !1 ? "yes" : "NO");
…
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make sim-run SIMULATOR=xcelium RUN_EXTMEM=1 VCD=0 INIT_MEM=0
Works well .
Activating VCD with
make sim-run SIMULATOR=xcelium RUN_EXTMEM=1 VCD=1 INIT_MEM=0
causes simulation to hang when s…
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Hello, I've been trying to run the HGDB vs code debugger and I'm unsure on how to proceed.
My process thus far:
Obtained the symbol table from hgdb-vitis.
Compiled the circuit with iverilog and…
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Hi,
I am trying to simulate the eth_mac_10g_fifo_32 module using the provided testbench. But getting this error . I have tried to find out what the problem is but could not get anything.
Here is the…
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To set the icarus timescale, a cmds.f file with the following content is created:
`+timescale+1ns/1ns
`
Then compile_args is set to:
`compile_args = ["-f /home/cmds.f"]
`
However, icarus c…
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Hi, I'm trying to integrate the PLIC core in a project and would like to simulate with Icarus (although not required).
One of the problems I encountered was that Icarus does not understand the key wo…